CPUs

15th Gen Intel Arrow Lake CPUs to Get L4 Cache “Adamantine”, Stacked Below the CPU Tile (Not Above)

Intel is working on 3D stacked processors and will soon have retail products based on this technology. Speaking to Tom’s Hardware, company CEO Pat Gelsinger explained that Team Blue will implement something rivaling AMD’s 3D V-Cache in future CPUs. Intel plans to leverage disaggregated cache dies in future processors, including 15th Gen Arrow Lake-S and potentially 16th Gen Lunar Lake as well. However, the implementation and use of the SRAM will vary.

When you reference V-Cache, you’re talking about a very specific technology that TSMC does with some of its customers as well. Obviously, we’re doing that differently in our composition, right? And that particular type of technology isn’t something that’s part of Meteor Lake, but in our roadmap, you’re seeing the idea of 3D silicon where we’ll have cache on one die, and we’ll have CPU compute on the stacked die on top of it, and obviously using EMIB that Foveros we’ll be able to compose different capabilities.
We feel very good that we have advanced capabilities for next-generation memory architectures, advantages for 3D stacking, for both little die, as well as for very big packages for AI and high-performance servers as well. So we have a full breadth of those technologies. We’ll be using those for our products, as well as presenting it to the Foundry (IFS) customers as well.

Pat Gelsinger, Intel CEO

In the past, we’ve seen several leaks quoting an L4 cache codenamed Adamantine or ADM. Unlike AMD’s V-Cache dies, the Adamantine or L4 cache die will sit directly below the CPU tile atop the interposer. This L4 cache will be used for various latency optimizations, caching data from the CPU, iGPU, and perhaps even the PCH. In addition to CPU gaming, this would also improve boot times, iGPU performance, and I/O latency.

According to Pat, Adamantine or L4 cache isn’t part of Meteor Lake but will be featured in future products. The CPU tile will be stacked atop the cache die using Foveros 3D stacking and EMIB interconnect. Intel will also offer this kind of 3D stacking and packaging technologies to its Foundry (IFS) customers, giving fabless chipmakers an alternative to TSMC’s CoWoS.

Areej Syed

Processors, PC gaming, and the past. I have written about computer hardware for over seven years with over 5000 published articles. I started during engineering college and haven't stopped since. On the side, I play RPGs like Baldur's Gate, Dragon Age, Mass Effect, Divinity, and Fallout. Contact: areejs12@hardwaretimes.com.
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