AMD’s Ryzen 8000 mobility family will be a big one, leveraging multiple core architectures and process nodes to satisfy the lucrative notebook and handheld markets. Among them, one particular lineup stands out. Strix Point will feature the first Ryzen processors to leverage a hybrid core architecture. Unlike Intel, AMD will use the same ISA for the P and E cores, the only difference between them being the L3 cache buffer.
The Zen 5 “P” cores will be backed by 32MB of L3 cache per CCD (8 cores), while Zen 5c “E” cores will cut it in half, bringing it down to 8MB per 8 cores. On TSMC’s 5nm-class node, Zen 4c is up to 40% smaller than the vanilla Zen 4 core. The Ryzen 8000 “Strix Point” family will allegedly consist of four Zen 5 and eight Zen 5c cores. Each Zen 5 core is paired with 1MB of L2 cache, the same as Zen 5c, bringing the total L2 cache to 4MB and 8MB, respectively.
As already explained, the four Zen 5 cores will share a 16MB L3 cache chunk, leaving the Zen 5c octet with half as much. The Ryzen 8000 APUs will be paired with a potent iGPU based on the RDNA 3.5 graphics architecture. We’re looking at 8 WGPs or 16 CUs for the higher-end chips. This translates to 1,024 shaders, 16 Ray Tracing Accelerators, and 32 AI units. With boost clocks of over 2.5GHz, we’re looking at console-grade compute throughput.
The next-gen Ryzen 8000 processors will feature a vastly upgraded AI Engine. Strix Point will pack up to 64 AIE Tiles, 4x as much as Phoenix. These mobility chips will natively support DDR5-6400 memory, with LPDDR5x-8533 variants planned. These APUs will be monolithic, and highly scalable, targeting 28W ultrabooks as well as 35-45W high-performance gaming notebooks. They’ll be manufactured using TSMC’s N4 process node.
