AMD Ryzen 8000 “Zen 5” Core Architecture Leaks Out: P-Cores, 16 Core CCDs, and More

AMD’s Zen 5 core architecture set to power the next-gen Ryzen 8000 processors has leaked out, courtesy of Moore’s Law is Dead. Codenamed Nirvana, the fifth iteration of the Zen microarchitecture makes substantial changes to both the front and the backend. The chipmaker’s x86 core roadmap promises a 10-15% IPC increase and the introduction of 512-bit FP units, low-power cores, and a new 16-core CCD (Zen 5 Dense).

The Zen 5 core has been beefed up from all sides, including the frontend, backend, memory sub-system, and cache. Starting from the top, we’ve got an improved branch predictor capable of “Zero bubble” conditional branches. This means that the branch predictor of Zen 5 can access the BTB without any penalties (mostly one RR) or bubbles. Speaking of the Branch Target Buffer, Zen 5 also upgrades its capacity and accuracy, which is crucial in conditional indirect branches.

The L1I data cache, an input cache has been increased to 48KB (from 32KB) 12-way with a 4-cycle latency. Similarly, the DTLB and the PWC have also been expanded for better address translation. Interestingly, the decoder seems untouched, but the dispatch queue has been widened from 6 to 8 micro-ops with support for op fusion. This allows two micro-ops from the same instruction to be treated as one at some points.

Coming to the backend, Zen 5 strengthens AMD’s already formidable Integer Execution. The ALU count has been increased from 4 to 6, paired with a larger Integer Scheduler. On the Vector/FP Side, 512-bit wide FP units have been added to improve AVX512 performance. The Load/Store Units haven’t been ignored either. Zen 5 can do 4 loads or 2 stores per cycle, up from 3 loads on Zen 4.

An early Epyc-based Zen 5 CPU (64 cores x2) allegedly scores 123K points in Cinebench R23, a 15% improvement over equivalent Zen 4 hardware. Keep in mind that this is an engineering sample with lower clocks. The final retail version will be even faster.

Zen 5 will come in two CCD variants: The traditional 8-core dies fabbed on TSMC’s 4nm node and a 16-core Zen 5c variant fabbed on 3nm. On “AM5” desktops, 16-core Zen 5, 32-core Zen 5c, and 8P +16E core variants are possible. The Epyc platform can accommodate up to 128 Zen 5 and 192 Zen 5c cores. In line with previous rumors, Zen 5 is expected to land in the first half of 2024.

Areej Syed

Processors, PC gaming, and the past. I have written about computer hardware for over seven years with over 5000 published articles. I started during engineering college and haven't stopped since. On the side, I play RPGs like Baldur's Gate, Dragon Age, Mass Effect, Divinity, and Fallout. Contact: areejs12@hardwaretimes.com.
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