A report from UDN claims that AMD’s Zen 5 architecture will leverage TSMC’s 3nm node, with mass production set to begin next quarter. Specifically, the rumor alleges that “the most critical core computing chip will be manufactured by TSMC using its 3nm process.” That’s using Google Translate, so take it with the necessary amount of caution. Either way, this implies that one of the dies from the Zen 5 family will be fabbed on N3, and it doesn’t have to be a Ryzen 9000 client die.
If the Ryzen 9000 processors land in the third quarter of this year, then N3 is highly unlikely. Production levels aren’t quite up there yet, but the prices are. It doesn’t go with AMD’s strategy of utilizing a process node for two generations, as we saw with the earlier 7nm and now 5nm-class nodes. The most likely scenario would be to keep an N3-based die for the high-margin Epyc/Instinct data center processors.
According to Bionic_Squash, the Zen 5 CCD will be fabbed on TSMC’s N4 node, while the Zen 5c CCDs will leverage a 3nm-class process. The latter will be used for the cloud-centric Epyc lineups (Bergamo NEXT) and may come to hybrid notebook designs later on.
