AVX-512 will be making its way back to Intel’s client processors as part of the AVX10 superset. And this time, these wide vector instructions will be supported across both Performance and Efficiency cores, allowing their use in future Core processors. The 6th Gen Xeon “Granite Rapids” family will be the first to support AVX10.1 (pre-enabling).
AVX 10.1 will be limited to the Xeon P-core processors, adding version-based enumeration and optional 512-bit Floating Point or Integer instruction support. AVX10.2 will be the big one, supporting new data movement, transforms, and type instructions along with 512-bit Floating Point and Integer support. To support AVX10 fully on both the P and E cores, the converged version will have a maximum vector length of 256 bits.
Of course, the existing AVX256 code will need to be recompiled to fully support AVX10. To promote this, Intel plans to roll out AVX10-optimized software from here on out.
