Intel 15th Gen Arrow Lake CPUs to Support 512-bit SHA and AI Instructions, AVX512 Still Missing

In a new update to its instruction extensions and features manual, Intel has announced the addition of a slew of neural network and encryption instructions to its upcoming 15th Gen Arrow Lake-S processors. Among the former, we’re mainly talking about mixed precision VNNI instructions, including AVX-VNNI-INT16 and AVX-VNNI-INT8. In terms of encryption and cryptography, we’re looking at SM3, SM4, and SHA512 instruction support for Arrow as well as Lunar Lake.

It’s worth noting that like that, like AVX512, SHA512 is a 512-bit SIMD instruction used for cryptography algorithms. SHA512 allows the use of SHA security keys up to 512 bits. Meanwhile, SM3 and SM4 are Arm-based encryption and decryption instructions yet to be natively supported on x86 processors.

Another instruction worth looking at is Linear Address Masking or LAM. It allows the software to use 64-bit memory addresses without translation on behalf of the MMU and add additional metadata in the extra bits.

To aid low-precision VNNI compute, Intel has also added the AVX-NE-CONVERT instruction which converts low-precision floating-point data like FP16 or BF16 to high-precision FP32. It is also capable of converting FP32 into the neural network-friendly BF16 format. Last but not least, you’ve got AVX-IFMA which adds non-AVX512 Integer Fused Multiple and Add.

Areej Syed

Processors, PC gaming, and the past. I have written about computer hardware for over seven years with over 5000 published articles. I started during engineering college and haven't stopped since. On the side, I play RPGs like Baldur's Gate, Dragon Age, Mass Effect, Divinity, and Fallout. Contact: areejs12@hardwaretimes.com.
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