An engineering sample of AMD’s next-gen hybrid processors “Strix Point” has been spotted, courtesy of Performancedatabases.com. The chip in question is a 12-core part with 4 P-cores and 8 E-cores. The former leverage the Zen 5 core architecture while the latter are based on the stripped-down Zen 5c design. The screenshots shared are from CPU-Z and HWiNFO, highlighting the basic specifications of the SKU.
The Zen 5 cores feature 48KB of L1D and 32KB of L1I cache. At 1MB per core, the L2 cache is the same as Zen 4 with 8MB L3 shared across four cores. The Zen 5c cores have considerably less cache per core. Packed in groups of four, we’re looking at 1MB of L2 cache per cluster, backed by 8MB of L3 cache for the entire set.
The clock speeds are incorrectly reported as 6.37GHz (boost) and 2.21GHz (average active clock), making them more or less irrelevant. The APU has a TDP of 45W which makes sense as it’s the successor to Phoenix 2, AMD’s first hybrid core design.
An interesting bit to note here is that despite a heterogenous processor with two different core clusters, AVX512 is officially supported on both. This is one of the primary advantages of leveraging a single ISA across both clusters.
Strix Point should arrive sometime in the second half of 2024. Expect a CES 2024 reveal, followed by a fall release if all goes according to plan.
