The latest LLVM/Clang update supports multiple future Intel CPUs and the AVX10.1 (pre-enabling) ISA. The 16th Gen Panther Lake (Core Ultra 3?) and Xeon Clearwater Forest processors are supported by LLVM/Clang 18.1 alongside the AVX10.1-256 and AVX10.1-512 instruction set architecture. The AVX10 ISA isn’t coming to either lineup, with Granite Rapids and its successor being the only processors to adopt the new standard.
The 16th Gen Pather Lake processors will succeed 15th Gen Arrow Lake (or perhaps an Arrow Lake Refresh). These will likely be called the Core Ultra 3 series CPUs, debuting in the notebook segment ahead of the desktop. The LGA1851 socket will be retained whenever it launches for the desktop and DIY markets.
The P-core architecture will be upgraded to Cougar Cove, while the Skymont E-core will be retained with minor changes. The compute tile will be fabbed on the 18A process node, making it even more likely a mobile family. It is rumored to feature 16 cores, including 4P, 8E, and 4 LPE cores. The notebook processors based on Panther Lake are expected in late 2025.
Clearwater Forest is the Xeon E-core equivalent of Panther Lake. Succeeding Sierra Forest in late 2025, it’ll cram up to 288 cores based on the Darkmont architecture (Skymont repurposed for cloud). Clearwater will square off against whatever succeeds the AMD Epyc Bergamo processors. The latter will be a Zen 5c-based design fabbed on a TSMC 3nm node with 256 or more cores.
Source: Phoronix.
Further reading:
Intel CPU Roadmap Update: 15th Gen ARL + LNL in 2024, Panther Lake in 2025 & Nova Lake in 2026
