AMD Ryzen 9000 “Zen 5” to Get Expanded AVX-512 Support with Upgraded FP Execution

The Zen 5 core expands the execution units, on the integer and floating-point ends. The registers are getting wider and so is the load/store

Premature support for AMD’s next-gen Zen 5 processors has landed in the GNU compiler collection. Initially shared on the AnandTech forums by member Bigos, the initial patch adds support for AVXVNNI, MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT, and PREFETCHI instruction sets. Most of these have existed on Intel chips since the days of Willow Cove (Tiger Lake), while PREFTECHI is expected to debut with Lion Cove (?).

Via: AnandTech forums

Vector Neural Network Instructions (AVXVNNI) should help accelerate neural network workloads still operated on the CPU, offering parity with Intel’s Sapphire and Emerald Rapids. Zen 5 reduces the cost of division/mod instructions thanks to improvements to the execution units. Additionally, the cost of DIVSS (Divide Scalar Single Precision), DIVSD (Divide Scalar Double Precision), SQRTSS (Square Root, Scalar, Single Precision), and SQRTSD (Square Root, Scalar, Double Precision) has also been reduced.

On the hardware side, the Zen 5 expands the execution pipelines on both the integer and floating point sides. These changes align with the MLID leak we reported last year. The Integer ALU pipelines have increased to 6 (previously 4), while an additional AGU boosts the load/store units (4, previously 3). Overall, we’ve got ten execution ports on the Integer Execution side (previously 8).

On the Floating Point side, the execution ports have been expanded to 512-bit wide. The patch indicates that all five FMUL/ADD units are 512-bit wide to support AVX-512 instructions, which is crazy. Intel designs consist of a single 512-bit FP unit. Of course, not all FP instructions will utilize the full 512-bit pipe, and many will be masked. Expanded EUs mean larger registers to sustain them, substantially larger if all are 512-bit wide. The fact that AMD made so many changes to the backend in a single generation is remarkable.

Areej Syed

Processors, PC gaming, and the past. I have written about computer hardware for over seven years with over 5000 published articles. I started during engineering college and haven't stopped since. On the side, I play RPGs like Baldur's Gate, Dragon Age, Mass Effect, Divinity, and Fallout. Contact: areejs12@hardwaretimes.com.
Back to top button