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AMD Ryzen 9000 Specs, Architecture & Pricing: A Look at the Zen 5 Processors

Updated: 26th July.

The first Ryzen 9000 processors are launching on the 8th of August, following a discrepancy in the first set of units shipped to OEMs and ODM partners. These include the Ryzen 5 9600X and the Ryzen 7 9700X, followed by the Ryzen 9 9900X and the 9950X on the 15th of August.

AMD Ryzen 5 9600XAMD Ryzen 7 9700XRyzen 9 9950XRyzen 9 9900X
Cores/Threads6/128/1616/3212/24
L2 Cache (per core)1 MB1 MB1 MB1 MB
L3 Cache (shared)32 MB32 MB64 MB64 MB
Boost Clock5.4 GHz5.5 GHz5.7 GHz5.6 GHz
PCIe Lanes (Gen 5)24242424
Memory SupportDDR5-8000DDR5-8000DDR5-8000DDR5-8000
TDP65W65W170W120W
ProcessTSMC 4nmTSMC 4nmTSMC 4nmTSMC 4nm
LaunchJuly 2024July 2024July 2024July 2024

The Ryzen 9000 desktop lineup will feature up to 16 cores (32 threads) spread across two 8-core CCDs, each packing 32MB of unified L3 cache, and 64MB total. The Zen 5 dies will be fabbed on TSMC’s 4nm (N4P) process. The top-end Ryzen 9 9950X will have a peak boost clock of 5.7 GHz and a TDP of 170W. The Ryzen 9 9900X reduces the TDP to 120W, while the lower-end SKUs are specced at 65W.

The Ryzen 9000 processors are expected to be cheaper than their predecessors by at least $25 to $50. This is to ensure that they look more appealing than the heavily discounted Ryzen 7000 stack:

  • The Ryzen 9 9950X should be priced at $649, $50 less than the launch price of the Ryzen 9 7950X.
  • The Ryzen 9 9900X is expected to cost $499, or $50 less than the Ryzen 9 7900X’s launch MSRP.
  • The Ryzen 7 9700X is said to cost between $349, making it $50 cheaper than the Ryzen 7 7700X.
  • The Ryzen 5 9600X should cost a bit under $299.

AMD Ryzen AI 300: Strix Point, Strix Halo & Kraken Specs

Update: AMD has officially announced the Strix Point processors. The specifications of the Ryzen AI 9 HX 370 and the Ryzen AI 9 365 are out. The former features 4x Zen 5 and 8x Zen 5c cores and a Radeon 890M GPU (16 CUs or 1024 cores). The latter incorporates 4x Zen 5 and 6x Zen 5c cores and a Radeon 880M GPU (12 CUs or 768 cores). Both will leverage the RDNA 3.5 graphics architecture and a 50 TOP NPU.

NameGraphics Model# of CPU Cores# of ThreadsMax. Boost ClockBase ClockGraphics Core CountAMD Ryzen AIDefault TDP
AMD Ryzen AI 9 HX 375AMD Radeon 890M1224Up to 5.1 GHz2 GHz16Available28W
AMD Ryzen AI 9 HX 370AMD Radeon 890M1224Up to 5.1 GHz2 GHz16Available28W
AMD Ryzen AI 9 365AMD Radeon 880M1020Up to 5 GHz2 GHz12Available28W

AMD’s official benchmarks paint an impressive picture of Strix Point. In content creation workloads (Cinebench, Blender, and Adobe Premiere Pro), the Ryzen AI HX 370 is up to 73% faster than Intel’s Core Ultra 185H Meteor Lake flagship.

In gaming, the HX 370 is 28-47% faster than the Core Ultra 185H, though this isn’t a surprise given AMD’s superior Radeon iGPU graphics architecture.

The Ryzen 9000 mobile family will be massive, consisting of Strix Point, Strix Halo, Kraken Point, Sonoma Valley, and Fire Range. These chips will feature an upgraded CPU, GPU, and NPU. The Zen 5 cores will be paired with the Zen 5c “E-cores,” marking the release of AMD’s first true hybrid core processors.

The RDNA 3.5 graphics architecture will debut, offering dGPU-level gaming performance at a much lower power budget. Strix Point will also feature a next-gen NPU based on the XDNA 2 architecture, offering 2-3x the inferencing throughput as Hawk Point.

  • 45-75W->
    • Strix Halo (chiplet-based): 16x Zen 5 on TSMC N4P: FP11.
      • GPU: 40x RDNA 3.5 CUs.
      • L2 Cache: 16MB (1MB per core).
      • L3 Cache: 64MB (shared).
      • NPU: 75T?
  • 15-54W->
    • Strix Point (hybrid, monolithic U/H): 4x Zen 5 + 8x Zen 5c on TSMC N4P: FP8.
      • GPU: 16x RDNA 3.5 CUs @ 2.6-2.7GHz.
      • L2 Cache: 12MB (1MB per core).
      • L3 Cache: 24 MB (16MB + 8MB).
      • NPU: 55T (overall 85 TOPS).
    • Kraken Point (hybrid, monolithic U/H): 4x Zen 5 + 4x Zen 5c on TSMC N4P: FP8.
      • GPU: 8x RDNA 3.5 CUs.
      • NPU: 45T?
  • 9-15W->
    • Sonoma Valley (monolithic U): 8x Zen 5c on Samsung SF4P: FP6.
      • GPU: 2x RDNA 3.5.
      • NPU: N/A.

The Ryzen 9000 mobile family will comprise the following lineups:

  • Strix Point: These CPUs will form the Ryzen AI 300 series, combining (up to) 4x Zen 5 and 8x Zen 5c cores in a monolithic design on the FP8 package.
    • The iGPU will feature (up to) 16x RDNA 3.5 Compute Units and a 55 TOP NPU unit. Strix will power ultrathin (U) and performance (H) notebooks in the 15-54W segments.
  • Strix Halo: Strix Halo will allegedly feature a chiplet design packing up to 16 Zen 5 cores (8C x2) and a beastly iGPU with 40 Compute Units (RDNA 3.5).
    • Like Strix Point, it’ll also feature a powerful NPU for AI workloads packaged on FP11. The TDP range will vary from 45W to 75W, targeting gaming and content creation notebooks (H).
  • Fire Range: This is a bit murky. Fire Range is supposed to be the successor to Dragon Range featuring repurposed AM5 “Granite Ridge” CPUs with reduced clocks and power limits.
  • Kraken Point: Kraken Point will resemble Strix Point, but reduce the core counts and TDPs, making it suitable for ultrabooks and convertibles. It will likely have a TDP range of 15-28W (U/H) and utilize the FP8 package.

AMD Epyc Turin Specs and Release Date

The Epyc Turin family will be much more diverse than Genoa consisting of Turin Dense, Turin-X, Turin Classic, Turin AI, and Sorano (succeeding Siena). Turin Classic will offer up to 128 Zen 5 cores for traditional server and data center clients while Turin Dense will serve the Cloud market with core counts of up to 160 (Zen 5c).

Like Genoa, Turin will retain the SP5 (LGA-6096) socket. The TDP of the “Classic” Zen 5 CPUs will vary from 200W on the lower-end SKUs to 400W on the flagship models. The L3 cache is unchanged at 32MB per CCD, implying a total Last Level Cache (LLC) of 384MB and 512MB for 96-core and 128-core variants, respectively.

Looking ahead, we’re very excited about our next-gen Turin family of EPYC processors featuring our Gen 5 core. We’re widely sampling Turin, and the silicon is looking great. In the cloud, the significant performance and efficiency increases of Turin position us well to capture an even larger share of both first and third-party workloads. In addition, there are 30% more Turin platforms in development from our server partners, compared to fourth-gen EPYC platforms, increasing our enterprise and with new solutions optimized for additional workloads. Turin remains on track to launch later this year.

Dr. Lisa Su, AMD CEO

The Epyc Turin “Dense” Zen 5c lineup will feature up to 160 cores and 320 threads. These are clocked at just over 2GHz for the “denser” flagship SKUs with an L3 cache of up to 320MB (32MB per 16-core CCD). As per rumors, there will be only three Turin Dense chips with TDPs of up to 500W. Turin Classic “Zen 5” and Dense “Zen 5c” are slated to land later this year.

Source: Moore’s Law is Dead.

Turin-X is expected in early 2025 with 1.536GB of L3 cache (3D V-Cache) and roughly the same core counts as Turin Classic. Turin AI should launch simultaneously with Zen 5c cores and an AI chiplet featuring a neural accelerator. Then there’s Sorano, a budget and power-efficient variant of Turin Dense with up to 64 cores and a TDP of 225W.

The Zen 5 Core Architecture

Zen 5 Front End

The Zen 5 core (codenamed Nirvana) is a major upgrade over Zen 4, with a reworked frontend, wider dispatch, and increased execution resources. The branch predictor has been optimized for “zero-bubble” conditional branches. This means there won’t be a pipeline delay when the core executes conditional branches.

The L1 BTB has been expanded from 1.6K to 16K, while the L2 “TAGE” BTB has grown from 7K to 8K entries. The Branch Target Buffer keeps track of the branches taken and the target address of the calculated instruction.

The decoder has been doubled in width, from 4-wide to 2x 4-wide, and can decode up to 8 instructions per cycle. The two 4-wide pipes are independent, and can simultaneously decode instructions. In SMT mode, each thread gets a 4-way decoder. The decoder is fed by a dual-ported instruction fetch with a bandwidth of 64 bytes per cycle (up from 32).

The OpCache holds up to 6K entries with 2x 6-wide streams capable of delivering up to 12 instructions to the dispatch unit. The OpCache associativity has also been increased by 33% to 16-way, with 6 fused instructions per entry. The Dispatch has been expanded from 6-wide to 8-wide, sending up to 8 micro-ops to the execution backend.

Zen 5 Backend

Zen 5 strengthens AMD’s already formidable Integer Execution. The integer scheduler has been consolidated into a unified queue with 88 ALU and 56 AGU entries. The rename buffer can now hold 240 register files and 192 flags. Two additional ALU ports have been added (4->6), and a fourth AGU port for address generation. The ROB is now capable of holding 448 entries.

On the Floating Point end, all four execution ports have been doubled in width to 512-bit to support AVX-512 instructions with a 2-cycle FADD, with two load/store register ports. The FP scheduler now consists of 3x 32-entry queues and a 96-entry non-scheduling queue. The register file has also doubled in width, from 192 to 384 entries.

The load/store bandwidth has increased to 2x 512b loads or 1x 512b store per cycle. It can also handle 4x 256b loads or 2x 256b stores. The queues have been expanded (by an unspecified amount). Zen 4 has a 136-entry load and 64-entry store queue. The L1D cache has been increased from 32 KB 8-way to 48 KB 12-way. The Data Translation Buffer has grown from 72 (L1) and 3072 (L2) to 96 and 4096, respectively. The L2 cache remains 1 MB but is now 16-way associative, with 2x the bandwidth.

AM5 800 Series Motherboards

The 800-series motherboards comprising four chipsets are scheduled to launch a few months after the Ryzen 9000 family. These include the X870E, X870, B850, and the B740. The X-skew will include PCIe Gen 5 support for the dGPU + NVMe and USB 4. B850 will feature Gen 5 for the NVMe, with certain premium boards including it for the dGPU. The B840 chipset will be limited to Gen 3, with only memory overclocking.

AMD Ryzen 9000X3D and Zen 5 V-Cache

The Ryzen 9000X3D processors (Zen 5 3D V-Cache) are expected to be revealed this fall, around the time of the Intel Arrow Lake-S launch. An October announcement seems imminent, depending on how and when the Core Ultra 200 series arrives.

Frequently Asked Questions

  • Will the Ryzen 9000 CPUs be compatible with existing AM5 motherboards (A620/B650/B650E/X670/X670E)?

AMD has officially confirmed that the AM5 socket will be supported through 2025. The 600-series motherboards are fully compatible with the Ryzen 9000 CPUs. Most board partners have already released firmware enabling support for the next-gen Zen 5 processors.

  • When will the Ryzen 9000 CPUs be available for purchase?

The Ryzen 5 9600X and the Ryzen 7 9700X will launch on the 8th of August, followed by the Ryzen 9 9900X and the 9950X on the 15th of August.

  • How fast will the Ryzen 9000 CPUs be compared to the 7000 series and Intel’s Raptor Lake offering?

The Zen 5 core architecture offers an average 16% IPC uplift over Zen 4. This translates to an impressive 10-50% lead over the Intel Core i9-14900K in content creation, and up to 23% faster framerates in gaming workloads.

  • How much will the Ryzen 9000 CPUs cost? The pricing?

The Ryzen 9000 processors should cost the same (or $25-50 lower) as the Ryzen 7000 chips at launch. That’s <$299 for the Ryzen 5, $349-399 for the Ryzen 7, and $499-699 for the Ryzen 9 SKUs.

AMD Zen vs Zen 2 vs Zen 3 vs Zen 4 vs Zen 5 Core Architecture: Road to Ryzen 9000

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