AMD is set to announce its Ryzen 9000 processors at Computex 2024 (next month). We covered everything we know about Zen 5 in an earlier post. The next-gen Ryzen processors will focus on single-threaded performance and cache bandwidth, leaving the core/thread counts unchanged. Zen 6 will tackle the multi-threaded performance targets. According to Moore’s Law is Dead, the Zen 6 core architecture will be finalized (taped out?) in the third quarter of this year.
Zen 6 will leverage TSMC’s 2nm-class process node, but there’s a catch. Not all lineups will be manufactured on the N2 node, leaving them for more mature nodes such as 3nm-class N3P or N3X. AMD will probably prioritize the server capacity for N2 to account for the high wafer pricing.
The YouTuber believes that Zen 6 has three variants: Standard, Dense Classic, and Client Dense. Client Dense is allegedly even denser than Dense Classic, but at the expense of efficiency. From what I can gather, Zen 6 “Standard” will be used for the mainstream Ryzen “P-cores” and the Epyc “Venice” processors, while Dense Classic and Dense Client are the cloud and PC variants of the E-core, respectively.
Zen 6 was initially going to retain the Zen 5 memory controller but has now been redesigned from scratch. The Execution Scheduler (consolidated and expanded on the Integer side in Zen 5) is also a brand-new design from the ground up. Ergo, Zen 6 looks like a major architectural rework.
The “Venice SP7” flagship is rumored to feature up to 8x Zen 6 CCDs or 256 cores, 16x DDR5-6400 memory channels, 128 PCIe Gen 5, and 64 Gen 6 lanes. Each CCD will be fabbed on a 2nm-class node and the IOD on a 4nm derivative. Each compute die can be swapped with an AI, NCD, or FPGA per the market need. More on this here.
