Intel’s switch to a hybrid core architecture aimed to improve multi-threaded performance and optimize the power efficiency of mobility designs. While the former has been somewhat successful, the latter has failed spectacularly. Intel’s 12th and 13th Gen CPUs are much less efficient than rival Ryzen offerings, with the E-cores often degrading performance in latency-sensitive tasks. So, what’s next for Team Blue?
Intel P-Core Roadmap 2026-28: The Lion, Cougar & Coyote
Lion Cove: The Lion Cove core architecture powers the P-cores in Intel’s Arrow and Lunar Lake processors. It expanded the core front-end, including the branch predictor, fetch, decoders, and op-cache. It split the execution backend into separate vector and integer pipelines.
Lion Cove has a much wider backend, including the ROB, rename, and retire buffers. The execution ports (excl. memory) have been doubled from 5 to 10, with a deeper DTLB and a three-level data cache. The Lion Cove compute dies are fabbed on TSMC’s N3B node.
Panther & Nova Lake: 2025-26
Cougar Cove (H2 2025): Cougar Cove is set to succeed Lion Cove on the mobility platform, powering the P-cores on the Panther Lake processors. Like Redwood Cove (Meteor Lake), it’ll be a minor architectural upgrade, focusing on the efficiency improvements from the node shrink:
- Panther Lake’s CPU tiles will be fabbed on Intel’s 18A or TSMC’s N2P process. Think of it as a “Tic.”
- It will be exclusive to notebooks and is scheduled to launch by the end of 2025.
Coyote Cove (H2 2026): Coyote Cove will power the P-cores on the Nova Lake platform. Like Lion Cove, it’ll be a major architectural change. Improved branch prediction, wider core, refined vector/integer compute, and faster data caches.
- Expect an IPC uplift of 10-15% over Lion Cove and higher core clocks.
- Nova Lake will integrate dual compute dies with up to 16 P-cores: (8P + 16E) + (8P + 16E).
- It’ll leverage TSMC’s N2P process node.
- Nova Lake is expected to launch in H2 2026.
Razer Lake: 2027
Griffin Cove (H2 2027): Griffin Cove will (reportedly) be Intel’s last P-core. Like Cougar Cove, it’ll be a slight architectural change, focusing on the node shrink or “Tik.”
- It’s likely going to be a mobile-only lineup, fabbed on the Intel 14A node.
- The Razer Lake processors featuring Griffin Cove are scheduled to release in late 2027.
Unified Core (2028): Intel is expected to release the first processors powered by the “Unified Core” in 2028 with Titan Lake. It’ll be the culmination of the P-core and E-core architectures into a singular all-around design:
- Given the significant investment Intel has made in hybrid core marketing, we can expect the P and E-core division to continue.
- Architecturally, however, it’d switch to a common ISA, relying on smaller caches and lower clocks to distinguish the E-cores.
- AMD’s classic and dense core division follows the same principles. Both use the same ISA, allowing uniform AVX512 and SMT support.
Further reading:
Intel Unified Core Architecture Details
Intel’s Unified Core architecture is expected to incorporate elements of the P and E-cores. However, it’ll be based on the scaled-up E-core architecture, specifically the Arctic Wolf design powering Nova Lake’s E-cores. This would greatly improve the PPA (Perf/Area) and efficiency aspects of the unified core design.
The Skymont core features a much wider front-end than traditional “Atom” E-cores: A 9-wide decode with a clustered design (3×3), but without an op-cache. I reckon we’ll see a dual-clustered 8-way decode with an op-cache in the unified core.
Unified Core: Backend
The backend would likely feature more vector registers, FMA, and FPDIV units for wider FP sets like AVX512. A multi-hierarchy data cache optimized for latency would be ideal, something similar to Lion Cove. A larger L3 cache for gaming workload is also highly probable.
Overall, I expect a design resembling AMD’s Zen 5 core with a clustered front-end, separate integer and floating-point execution, a large vector register, and a robust memory subsystem.
SMT, AVX512 & Node
SMT and AVX512 support are almost certainly going to make a comeback. An IPC uplift of 10-15% over Griffin Cove would be ideal. Rumors suggest that the Titan Lake CPU tile will be fabbed on Intel’s 14A node, but it could also be outsourced to TSMC’s 1nm/1.5nm node.
Sources: SiliconFly, Moore’s Law is Dead.
